The present invention relates to a leadless chip carrier apparatus. More particularly, the present invention relates to a leadless chip carrier apparatus suitable for high power, high frequency digital integrated circuits, hereafter referred to as logic components.
The implementation of ultra high speed processors, e.g. employing system clock rates above one hundred million cycles per second (100 MHz), requires advances in the use of subnanosecond logic components, transmission line design, the development of new packaging and logic board design, as well as fabrication techniques suitable for high speed systems. Examples of low or moderate speed logic device technology currently available are low power metal oxide semiconductor (MOS) technologies and the conventional and enhanced speed versions of transistor-transistor logic (TTL). In addition, there are several families of ultra high speed logic such as emitter coupled logic (ECL) and current mode logic (CML) which are currently fabricated with silicon technology.
The ultra high speed logic families such as ECL and CML demonstrate considerable speed and performance advantages over the more familiar TTL and MOS logic families. Even higher performance logic devices relying upon the electrical properties of gallium arsenide are now becoming available. However, the ultra high speed logic families require the use of transmission line concepts for interconnections between logic components so that the speed of these latter devices can be effectively utilized. In addition, there is often the need for a greater heat dissipation capability due to the greater power requirements of the ECL and CML families. Consequently, the methods for attaching individual logic components to a circuit board or the like are also becoming increasingly critical in the design of high performance computers employing these logic families.
Traditionally, logic components have often been packaged and mounted on printed circuit boards by the use of dual in-line packages (DIP). In such packaging methods, a logic component or die is usually encapsulated in either a ceramic or plastic housing having electrical connectors extending generally downward therefrom for suitable attachment to a circuit board. Electrical leads, also encapsulated in the DIP housing, extend from the external electrical connectors to the corresponding electrical contact points on the logic die sealed inside the encapsulant.
When high speed logic components have been packaged in dual in-line packages, the resultant performance of such components when so packaged has not achieved the performance expectations or predictions for the high speed logic components as stated by the manufacturers of such components. The Applicants in analyzing this shortfall in performance have discovered that due to the substantial lengths of these internal electrical leads or interconnects and the varying configuration of the leads, an unacceptable signal delay occurs in the interconnect lines. Further, it has been impossible to maintain a transmission line environment in these interconnects, which results in signal interference and waveform degradation. Consequently, the effective speed of the logic component cannot be fully utilized.
Delay in the interconnects is partially due to the series inductance of the internal leads and the proximity or configuration of the wires to one another. In attempting to decrease signal rise and fall times, signals are driven at relatively high current levels to enable high speed logic operations to occur. As more current is provided, the series inductance of the interconnects, which is a function primarily of their length, resists the rapid changes in current flow by creating a resisting voltage spike. Typically, the longer the wire interconnect, the more series inductance which is present. Additionally, the signal interconnects which lie in close proximity function as capacitors relative to one another, thereby creating a parasitic shunt capacitance which forms a signal crosstalk path between adjacent lines and causes a disruption in the transmission line characteristics of the interconnects between components. These combined inductive and capacitive parasitics hinder or delay the signal in the interconnects and are significant factors in the design of high speed processor systems.
In addition, every interconnect between integrated circuits has a characteristic impedance. If the transmission line or interconnect is not terminated with a matching impedance, signal wavefronts will be reflected, causing voltage distortion of the signal. At every location along a transmission line at which a connection is made to an integrated circuit, the characteristic impedance of the line is thereby modified. This impedance discontinuity creates the voltage reflections described above. Therefore, it is important to provide either a low shunt capacitance on the input of each package lead, or better yet, a controlled impedance transmission line environment all the way to the integrated circuit inside the package. This will avoid voltage ringing following the rising and falling edges of the signal caused by a succession of positive and negative reflections on an interconnect line in a non-transmission line environment.
In addition, dual in-line packages are very large structures which prevent tight packing of integrated circuits on a logic board. In an effort to overcome the packing density problem, leadless chip carriers have been developed. However, although these carriers also have somewhat more favorable electrical characteristics for high power, high speed logic components such as ECL or Gallium Arsenide logic than do dual in-line packages, these improvements are accidental rather than purposeful, and leave much room for further performance improvements.
Firstly, commercial leadless chip carriers are designed to be mounted on circuit boards with their ceramic surfaces in direct contact with the printed circuit board. As a result, air cooling, heat pipe cooling or cold plate cooling of currently available leadless chip carriers is not feasible. Efficient air cooling or heat pipe cooling of leadless chip carriers, however, is feasible wherein the carrier is mounted with the ceramic surface facing upward from the circuit board and the logic die cavity, covered by a suitable cover portion, facing the circuit board.
Currently, most commercial leadless chip carriers cannot be inverted in a cover down position for several reasons. The covers extend beyond the surface of the leadless chip carrier so as to raise the leadless chip carrier above the face of the circuit board, thereby preventing electrical contact between the chip carrier and the circuit board. Furthermore, the vertical electrical contact paths along the edges of the chip carrier, referred to as castellations, typically utilized in currently available leadless chip carriers, must be insulated near their upper ends to prevent short circuits between the castellations and the leadless chip carrier cover. Thus, if the leadless chip carrier is inverted, it is impossible to achieve electrical contact between the metalized, conducting castellations and the circuit board. Cooling of the logic components packaged in conventional chip carriers has been attempted by providing a suitable heat sink in the core of the circuit board, or by providing a series of conduits within the board for the passage of a coolant therethrough. However, such boards are expensive to manufacture and the design, fabrication and redesign cycles are lengthy.
Yet another problem associated with presently available leadless chip carriers is the use, during chip carrier manufacture, of metalized "plating fingers" to provide conduction paths for the flow of DC current required in the electroplating step of the chip carrier assembly process. The metalized plating fingers are utilized during the plating process to assure proper formation of the signal line traces which extend from the electrically conductive castellations at the outside edge of the carrier inwardly toward the cavity of the carrier wherein the logic die is suitably attached. The Applicants have discovered that the electroplating fingers increase the shunt capacitance between adjacent signal lines and also to the AC ground planes within the chip carrier, thereby degrading the electrical performance of the chip carrier.
Furthermore, the Applicants have discovered that the configuration of present leadless chip carriers does not effectively minimize signal crosstalk or shunt capacitance problems between adjacent signal leads for high speed operation, and presently available chip carriers do not provide adequate transmission line environments wherein the signal leads have a controlled, low level impedance, and there is also no mechanism for terminating the signal leads close to the integrated circuit with an appropriate matching impedance. As a result, signal reflections are created which limit the maximum frequency at which the high speed logic components enclosed therein can function.
Also, the Applicants have discovered that presently available leadless chip carrier packaging techniques do not provide for adequate electrical and electromagnetic isolation of the logic components packaged therein from outside sources, and vice versa, and current fluctuations caused by sudden power demands, which occur when an integrated circuit switches logic states, are not properly alleviated in presently available leadless chip carrier designs.
Furthermore, methods of attaching the leadless chip carriers to the circuit board from both electrical and structural standpoints are not adequate in view of the high operating temperatures and corresponding expansion/contraction fluctuations to which the chip carriers are subjected.
These and many other problems are solved by the present invention.